Below are a number of Guideline Rules to follow and keep in mind when designing PCBs. These are general rules that apply for ACME PCB Assembly.

Board Size: maximum PCB 18.5 inch x 14 inch for SMT assembly.

Board Thickness: 20mil to 160mil for SMT assembly

Fiducial Mark: Fiducial is required to applied to PCB. Please go Fiducial Mark requirement for more information about Fiducial Mark.

Solder Mask: PAD CAP Outer layers are recommended. If used, solder mask clearance is required around all surface mount and through hole pads, tooling holes, shield contact areas, fiducials, and any areas where electrical contact or soldering is required. Check board fabricator for guidelines.

Tooling Holes: Tooling holes are required for positioning the PWB in machines and fixtures needed to process the board (e.g. drill machines, routing fixtures, auto insertion equipment and test fixtures). The configuration of the holes must be (4) 0.125″ + 0.002″ / -0.000″ diameter holes, unplated, in each corner of the board and 0.200″ from the edges. A component free area of approximately 0.400″ from the center of the hole must be maintained because of tooling contact with the board and limitations on auto placement insertion heads (see Figure 2-3). These requirements may vary for insertion machines, therefore tooling holes and restricted areas should be verified.

SMT reflow PAD width and length.

0201 chips: The reflow pad width will be equal to the component termination width + 0.005″. The reflow pad length will be the dimension of the termination band plus a 0.010″ extension plus a 0.001″ overlap. The pad to pad spacing will be the component length minus 2X the termination band dimension minus 0.002″ overlap. FOR EXAMPLE, a component with a 0.020″ body length, 0.010″ termination width, and 0.005″ termination band, will need a pad 0.016″ long, 0.015″ wide, and a pad spacing of 0.008″

0402 CHIPS: The reflow pad width will be equal to the component termination width + 0.010″ (see Figure 3-2). The reflow pad length will be the dimension of the termination band plus a 0.015″ extension plus a 0.002″ overlap (see Figure 3-2). The pad to pad spacing will be the component length minus 2X the termination band dimension minus 0.004″ of overlap. FOR EXAMPLE, a component with a 0.040″ body length, 0.020″ termination width, and 0.010″ termination band, will need a pad 0.027″ long, 0.030″ wide, and a pad spacing of 0.016″.

0603 AND 0805 CHIPS: The reflow pad width will be equal to the component termination width + 0.010″ (see Figure 3-3).The reflow pad length will be the dimension of the termination band plus a 0.020″ extension plus a 0.002″ overlap (see Figure 3-3). The pad to pad spacing will be the component length minus 2X the termination band dimension minus 0.004″ of overlap. FOR EXAMPLE, a component with a 0.080″ body length, 0.050″ termination width, and 0.015″ termination band, will need a pad 0.037″ long, 0.060″ wide, and a pad spacing of 0.046″.

1206 CHIPS:The reflow pad width will be equal to the component termination width + 0.010″ (see Figure 3-4). The reflow pad length will be the dimension of the termination band plus a 0.025″ extension plus a 0.002″ overlap (see Figure 3-4). The pad to pad spacing will be the component length minus 2X the termination band dimension minus 0.004″ of overlap. FOR EXAMPLE, a component with a 0.120″ body length, 0.060″ termination width, and 0.020″ termination band, will need a pad 0.047″ long, 0.070″ wide, and a pad spacing of 0.076″.

TANTALUM CAPACITORS: The reflow pad width will be equal to the component termination width + 0.010″ (see Figure 3-5). The reflow pad length will be the dimension of the termination area or leg plus a 0.025″ extension and a 0.002″ overlap (see Figure 3-5). The pad to pad spacing will be the component length minus 2X the termination leg dimension minus 0.004″ of overlap. FOR EXAMPLE, a component with a 0.235″ body length and termination length and width of 0.035″ X 0.085″, will need a pad 0.062″ long, 0.095″ wide, and a pad spacing of 0.161″.

SOIC: The reflow pad width will be ½ the lead pitch. The reflow pad length to be twice the lead foot length. The pad to pad spacing shall be ½ the lead pitch. Using the nominal dimensions of the component heel and toe extensions of 0.010″ – 0.020″ (0.010″ minimum) is required on the inside and outside of the pad for formation of the solder fillet. A larger heel may cause an excess solder condition on the inside of the lead reducing flexibility and increasing stresses on the solder joint

PLCC: The reflow pad width will be 1/2 the lead pitch. A pad 0.025″ wide is recommended for 0.050” lead pitch. The reflow pad length to be the nominal dimension of component lead + 0.010″ – 0.020″. A smaller extension may experience shadowing problems. Larger extensions have no advantage. The pad to pad spacing to be ½ the lead pitch.

COMPONENT SPACING: Component to component spacing is critical to soldering, rework, test and automated assembly. If components are placed too close together, the placement head of pick and place machines may interfere with other components requiring manual placement of some parts. Also, any of these conditions may cause a longer more costly assembly process and less reliable product. When placing chip components on the bottom of a board in a staggered pattern, a minimum spacing of 0.100″ is required to insure that shadowing and unsoldered terminations do not occur.

Care should be taken when designing with new or non-standard parts to provide the clearance required for assembly, rework and test. Generally the component to component spacing will be 1X the component height (preferred) or 1/2 the component height (minimum). Manufacturing engineering or the assembly vendor should be consulted when questions of spacing arise.

CAPACITOR PLACEMENT : As an aid to assembly, all polarized capacitors will be placed with the positive end to the right or down. The polarity will be indicated on the silkscreen by a plus or other indicator (i.e. bar) on the package outline. Chip decoupling capacitors on the top or bottom of the board will be placed perpendicular to SOICs and the solder flow. They will be placed as close as practical to the power pin of the IC.

COMPONENTS NOT RECOMMENDED FOR BOTTOM PLACEMENT : Some types of components are sensitive to the higher temperatures of wave soldering and should not be used on the bottom of boards where the solder wave would contact the component. Other types of components may not be suited to wave solder because of their lead configurations and size. The following is a list of components to avoid placing on the bottom of a board to be wave soldered:

Large body chip caps, package types 1812 and 1825 may crack when exposed to wave solder. Memory and static ram chips which may be damaged by high temperatures. The 1206 should be the smallest package size used on the solder side of the board. Smaller packages such as the 0805 are not well suited for epoxy application and wave solder. PLCCs as the lead configuration is not suited to wave solder. SOTs do not solder well due to leads being too close to component body.

TRACE ROUTING TO COMPONENT LANDS: Large traces connecting to a component land may cause heat to migrate away from the component termination resulting in poor solder joints. In cases where solder mask is not used, solder may flow away from the component termination causing an open solder joint. Necking the trace down as it enters the land prevents the solder and heat from migrating away from the pad and helps to thermally balance the land pattern. The trace should be a maximum of 0.010″ wide connecting to the pad and a minimum of 0.010″ long from the pad to a large trace. If the circuit design requires a wide trace to be connected to component lands, the traces connecting both lands should be the same width and the smallest possible dimension.

When connecting component pads to large ground traces, or wide high current conductors, the traces must be necked down and balanced to prevent the migration of heat (and solder if solder mask is not used) to large conductor areas. More than one trace may be used to connect ground planes and large traces to land patterns. The traces should be a maximum of 0.010″ wide connecting to the pad and a minimum of 0.010″ long from pad to large trace or plane.

Signal traces should connect to component pads using one trace per pad, preferably connecting to the outside or inside edges of the pads in a symmetrical manner. When using solder mask on the board, the angle and location of the connecting traces are not as critical as non-solder masked designs. Generally any routing which keeps the amount of trace connecting the component pads balanced will be acceptable.

VIA ROUTING GUIDELINES: Test via spacing will be 0.100″ preferred, 0.050″ acceptable. Refer to Section 7 regarding test requirements for other pad to pad spacing requirements. Do not place vias under axial through hole components as the component may be damaged during soldering when solder flows up through the via hole. Do not place vias in a location where it would be possible to insert a component incorrectly. For example: 0.100″ away from each end of a sip package. The placing of vias under chip components on wave soldered assemblies is not recommended, as solder flowing up through the via may lift or break the component, or possibly short a component to pad. If the chip component is located on the solder side of the board, avoid placing vias under or near the component where it may interfere with areas used to epoxy the component to the board.

Vias connecting to a component pad shall have a minimum clearance of 0.010″ from via edge to component land edge and maximum trace width of 0.010″.Spacings under 0.010″ are not recommended but may be useful on extra dense designs. If vias are to be placed closer than 0.010″ to a component pad, they must be covered with solder mask.

Vias not connecting to component pads will have a minimum clearance of 0.025″. When the PCB is to be wave soldered, via clearance to component pads on the solder side of the PCB will be 0.040″ if the via is placed before or after the pad in the direction of solder wave.

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